`timescale 1 ns / 10 ps
module div2( A, B, D, R, ok);
   parameter n = 32;
   parameter m = 16;
input [n-1:0] A, B; 
 output [n+m-1:0] D;
 output [n-1:0] R;
 output ok;
 
 reg [n+m-1:0] D;
 reg [n-1:0] R;
 reg ok;
always @(*)
begin
    D={{A/B},16'h0};
    R=A%B;
    ok=1;
end

endmodule

module tb_div2;
parameter n = 32;
parameter m = 16;
   
reg [31:0] A;
reg [31:0] B;
wire [n+m-1:0] D;
wire [n-1:0] R;
wire ok;

div2 UDIV (A, B, D, R, ok);

initial
begin
 
    A=32'h12153524;
    B=32'h00000001;

end 
endmodule